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INTEGRATED CIRCUITS
PCA9504A Glue chip 4
Product data Supersedes data of 2003 Nov 10 2004 May 11
Philips Semiconductors
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
platforms based on Intel(R) processors and chipsets that require additional external circuitry in order to function properly. It is used on entry servers/workstations (840 and 860 chipsets), high-end desktops (820 and 850 chipsets), as well as mid range (815, 830 and 845 chipsets) and low-end (810 chipset) motherboards. Some of these functionalities include meeting timing specifications, buffering signals, and switching between power wells. The PCA9504A Glue Chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin TSSOP device. The Glue Chip 4 typically resides on the motherboard close to the I/O controller Hub (ICH) and is optimized for the Intel 82801BA I/O controller hub (ICH2).
FEATURES
* Dual, Strapping, Selectable Feature Sets * Audio-disable Circuit * Mute Audio Circuit * 5 V reference generation * 5 V standby reference generation * HD single color LED driver * IDE reset signal generation/PCIRST# buffers * PWROK (PWRGD_3V) signal generation * Power Sequencing / BACKFEED_CUT * Power Supply turn on circuitry * RMSRST# generation * Voltage translation for DDC to VGA monitor * HSYNCH / VSYNCH voltage translation to VGA monitor * 3-state buffers for test * Extra GP Logic gates * Power LED Drivers * Flash FLUSH# / INIT# circuit * 5 V I2C to 3.3 V SMBus conversion to 400 kHz * Requires both 3.3 V and 5.0 V operating voltages * 0 to +70 C operating temperature range * ESD protection exceeds 1000 V HBM per JESD22-A114 and
750 V CDM per JESD22-C101
PIN CONFIGURATION
VREF3IN V_5P0_STBY V_3P3_STBY
GPO_FLUSH_CACHE/GP1_IN
1 2 3 4 5 6 7 8 9
56 GP3_OUT 55 GP3_IN 54 STRAP 53 VCCP_VREF 52 VSYNC_5V 51 HSYNC_5V 50 VSYNC_3V 49 HSYNC_3V 48 REF5V_STBY 47 AUD_SHDN 46 MUTE_AUD 45 VREF5IN 44 REF5V 43 GND 42 RSMRST 41 TEST_EN 40 GRN_LED 39 YLW_LED 38 YLW_BLNK 37 GRN_BLNK 36 SLP_S5 35 SCK_BJT_GATE 34 PWRGD_3V 33 FPRST 32 PWRGD_PS 31 FLUSH_OUT_FWH 30 LATCHED_BACKFED_CUT 29 GND
A20M/GP1_INB INIT/GP1_INA
FLUSH_OUT_CPU/GP1_OUT
INIT_OUT/GP2_OUT CLK_IN
SEL_33_66 10 GND 11 PCIRST 12 PCRIST_OUT 13 AUD_EN 14 AUD_RST 15 IDE_RSTDRV 16 3V_DDCSCL 17 5V_DDCSCL 18 3V_DDCSDA 19 5V_DDCSDA 20 CPU_PRESENT 21 SLP_S3 22 PS_ON 23 HD_LED 24 PRIMARY_HD 25
* Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
* Package offered: TSSOP56
DESCRIPTION
The PCA9504A Glue Chip 4 is a highly integrated and cost-efficient custom ASIC that reduces logic part count, overall component cost, and board space requirements for PC designers and manufacturers. The Glue Chip 4 supports the latest generation of high-volume
SCSI 26 SECONDARY_HD 27 BACKFEED_CUT 28
SW00578
ORDERING INFORMATION
PACKAGE 56-Pin Plastic TSSOP TEMPERATURE RANGE 0 C to +70 C ORDER CODE PCA9504ADGG TOPSIDE MARK PCA9504ADGG DRAWING NUMBER SOT364-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2004 May 11
2
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
PIN DESCRIPTION
PIN(S) 1 2 3 4 5 6 7 8 9 10 11, 29, 43 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 3I P P 3IU REF REF 5V OD 5V OD 3I 3IU G 3I 3O 3IU 3O 5O 3IOD 5IOD 3IOD 5IOD 3IU 3I 5V OD 5V OD 5IU 5IU 5IU 5V OD 5O 5V OD 5IU 5IU 3O 5V OD 3I 3IU 3IU 5V OD 5V OD 5ID 3O AO 5I 3IU 5O AO 3I VREF3IN V_5P0_STBY V_3P3_STBY GPO_FLUSH_CACHE / GP2_IN A20M / GP1_INB INIT / GP1_INA FLUSH_OUT_CPU / GP1_OUT INIT_OUT / GP2_OUT CLK_IN SEL_33_66 GND PCRIST PCRIST_OUT AUD_EN AUD_RST IDE_RSTDRV 3V_DDCSCL 5V_DDCSCL 3V_DDCSDA 5V_DDCSDA CPU_PRESENT SLP_S3 PS_ON HD_LED PRIMARY_HD SCSI SECONDARY_HD BACKFEED_CUT LATCHED_BACKFEED_CUT FLUSH_OUT_FWH PWRGD_PS FPRST PWRGD_3V SCK_BJT_GATE SLP_S5 GRN_BLNK YLW_BLNK YLW_LED GRN_LED TEST_EN RSMRST REF5V VREF5IN MUTE_AUD AUD_SHDN REF5V_STBY HSYNC_3V SYMBOL 3.3 V input 5 V system standby power supply 3 V system standby power supply GPO from SIO / ICH2 / Buffer 2 input A20M signal from ICH2 / NAND 1 input B INIT signal from the ICH2 / Buffer 1 input A Open drain signal, goes to the CPU / NAND 1 output Delayed INIT signal into the CPU / Buffer 2 output Either 33MHz or 66MHz clock, based on SEL_33_66 pin Strapping option for 33MHz or 66MHz CLK_IN Ground PCI reset signal Copy of PCRIST, increased drive-strength Audio enable input (GPO from ICH2 / SIO) Audio reset output IDE reset output, 5 V push/pull DDCSCL input/output 3.3 V side DDCSCL input/output 5 V side DDCSDA input/output 3.3 V side DDCSDA input/output 5 V side CPU present signal from the processor Signal from ICH2 for transitioning to the S3 power state Power supply turn-on signal Hard drive front panel LED output IDE primary drive active input SCSI drive active input IDE secondary drive active input Signal used for STR circuitry Signal used for STR circuitry Open drain signal, goes to the FWH Power good signal from power supply Reset signal from the front panel 3.3 V power good output Gate signal from the SCK BJT in suspend to RAM Signal from the ICH2 for transitioning to the S5 power state Power LED input, from SIO GPIO Power LED input, from SIO GPIO Power LED output Power LED output Test enable, 100K internal pull-down to GND Reset for the ICH2 resume well Highest system supply reference voltage 5V system primary supply input Signal from SIO to mute audio on power up/down Signal to audio amp to signal shutdown Highest system standby voltage HSYNCH input from chipset video FUNCTION
2004 May 11
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
PIN DESCRIPTION CONTINUED
PIN(S) 50 51 52 53 54 55 56 3I 5O 5O AI 3IV/3O 5I 5V OD VSYNC_3V HSYNC_5V VSYNC_5V VCCP_VREF STRAP GP3_IN GP3_OUT SYMBOL HSYNCH output to monitor VSYNCH output to monitor Analog voltage reference for determining INIT/A20M input thresholds Strapping option for GP or FLUSH mode (internal pull-up resistor) Note 1 Generic logic gate 3 input Generic logic gate 3 output FUNCTION VSYNCH input from chipset video
NOTE: 1. The pin is internally pulled up to default to FLUSH mode. TYPE 3I 3IU 5I 5IU 5ID P G 3O 5O 3V OD 5V OD AO AI 3IOD 5IOD REFL 3.3 V input signal 3.3 V input signal with internal pull-up 5 V input signal 5 V input signal with internal pull-up 5 V input signal with internal pull-down Power (input) Ground (input) 3.3 V output signal 5 V output signal 3.3 V open-drain output signal 5 v open-drain output signal Analog output Analog input 3.3 V input/output open-drain 5 V input/output open-drain Input voltage levels referenced to VCCP_VREF DESCRIPTION
FUNCTION TABLES
Strapping Selection Pin STRAP (pin 54)1 1 No connect 1 No connect 1 No connect 1 No connect 1 No connect 0 GND 0 GND 0 GND 0 GND 0 GND FLUSH FLUSH FLUSH FLUSH FLUSH GP GP GP GP GP MODE1 GPO_FLUSH_CACHE (4) A20M (5) INIT (6) FLUSH_OUT_CPU (7) INIT_OUT (8) GP2_IN (4) GP1_INB (5) GP1_INA (6) GP1_OUT (7) GP2_OUT (8) PIN NAME & (PIN NUMBER)
NOTE: 1. The pin is internally pulled up to default to FLUSH mode.
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
TYPICAL APPLICATION
GLUE 4 INPUTS PIN 1 2 3 4 5 6 9 10 12 14 17 18 19 20 21 22 25 26 27 32 33 36 37 38 41 45 46 49 50 53 54 55 FUNCTION VREF3IN 5VSB 3VSB GP2_IN GP1_INB GP1_INA CLK_IN SEL_33_66 PCIRST* AUD_EN 3V_DDCSCL 5V_DDCSCL 3V_DDCSD A 5V_DDCSD A CPU_PRESENT* SLP_S3* PRIMAR Y_HD* SC5I* SECOND AR Y_HD* PWRGD_PS FPRST* SLP_S5* GRN_BLNK YL W_BLNK TEST_EN VREF5IN MUTE_A UD* HSYNCH_3V VSYNCH_3V VCCP_VREF STRAP GP3_IN
V_3P3_STBY IN
V CC
V CC 3
1 k
10 k
10 k
GLUE CHIP 4
IN IN IN IN GPO_FLUSH_CACHE_PU* H_INIT_PU* P_PCIRST* TP_GLUE4_DDCSOL_3V IN IN IN CK_66M_GLUE CPU_PRESENT* IDE_PRI_ACT* NC IN IN IDE_SEC_ACT* GPIO_A UD_EN NC TP_GLUE4_TESTEN_41 GLUE4_SEL_33_66_R TP_GLUE4_DDCSD IN PWRGD_PS TP_GLUE4_DDCSD IN GLUE_FP_RST_R* TP_GLUE4_DDCSCL_5V A_3V A_5V 4 6 12 17 8 21 25 26 27 14 47 41 10 20 32 19 33 18 36 22 37 38 49 50 5 48 53 55 PWRGD_PS HAS WEAK GPO_FLUSH_CACHE/GP2-IN INIT/GP1_INA PCIRST 3V_DDC5CL CLK_IN CPU_PRESENT PRIMAR Y_HD SCSI SECOND AR Y_HD AUD_EN AUD_SHDN TEST_EN SEL_33-66 5V_DDCSD A PWRGD_PS 3V_DDC5D A FPRST 5V_DDCSCL SLP_55 SLP_S3 GRN_BLNK YLW_BLNK HSYNC_3V VSYNC_3V A20M/GP1_INB REF5V_STBY VCCP_VREF GP3_IN VREF5IN VREF3IN V_5P0_STBY V_3P3_STBY REF5V HD_LED PCIRST_OUT AUD_RST MUTE_A UD SCK_BJT_GA TE FLUSH_OUT_FWH FLUSH_OUT_CPU/GP1_OUT INIT_OUT/GP2_OUT IDE_RSTDR V BACKFEED_OUT LATCHED_BACKFEED_OUT PWRGD-3V PS_ON RSMRST YL W_LED GRN_LED HSYNC_5V VSYNC_5V STRAP GP3_OUT GND GND GND 45 1 2 3 44 24 13 15 46 35 31 7 8 16 28 30 34 23 42 39 40 51 52 54 56 11 29 43 GLUE4_VREF5IN_R GLUE4_VREF5IN_R V_5P0_STBY V_3P3_STBY V_REF5V HD_LED* P_RST_SLO TS_R* TP_A UD_RST* MUTE_A UD_PNI* TP-SCK-BJT_GA TE_ENABLE TP_GLUE4_FLUSH_OUT_FWH TP_GLUE4_GP1_OUT TP_GLUE4_8 IDE_RST* BACKFEED_CUT VREG_BACKFEED_U4 PWRGD_3V PS_ON* RSMRST* GPIO_YL W_BLNK_HDR GPIO_GRN_BLNK_HDR TP_GLUE4_HSYNC5V TP_GLUE4_VSYNC5V GLUE4_STRAP PWRGD_PS_BUFF OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OUT V_3P3_STBY IN
1 k
IN IN IN IN
SLP_S5* SLP_S3* GPIO_GRN_BLNK GPIO_YL W_BLNK TP_GLUE4_HSYNC3V TP_GLUE4_VSYNC3V
IN V_383_STBY IN OUT
AUD_MIDI_OUT_B_PU V5REF_SUS VCCP_VREF
100 49.9 k
INTERNAL PULL-UP
IC
10 k
SW01083
Figure 1. Typical application
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
ABSOLUTE MAXIMUM RATINGS1
LIMITS SYMBOL V_5P0_STBY V_3P3_STBY VI (5V) VO (5V) VI (3.3V) VO (3.3V) SPD ESD TSTG TOTR PARAMETER DC 5.0V supply DC 3.3V supply DC input voltage (5 V pins) Output voltage range (5 V pins) DC input voltage (3.3 V pins) Output voltage range (3.3 V pins) Supply power dissipation Static Discharge voltage Storage temperature range Operating Temperature Range 2000 -55 0 +150 70 Note 2 Note 2 Note 2 Note 2 CONDITION -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 MIN +6.0 +6.0 V_5P0_STBY+0.5 V_5P0_STBY+0.5 V_3P3_STBY+0.5 V_3P3_STBY+0.5 100 MAX V V V V V V MW V C C UNIT
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under "recommended operating condition" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VDD3 VDDL VI VO TA PARAMETER DC 3.3 V supply voltage DC 2.5 V supply voltage DC input voltage DC output voltage Operating ambient temperature range in free air CONDITIONS 3.0 4.75 0 0 0 MIN MAX 3.6 5.25 VDD3 VDDL VDD3 +70 UNIT V V V V C
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
DC CHARACTERISTICS
V_5P0_STBY = 5 V 5%; V_3P3_STBY = 3.3 V 10% LIMITS SYMBOL STRAP VIH VIL IIH VOL VOH IIL AUD_EN VIH VIL IIL IIH PCIRST VIH VIL IL Hys MUTE_AUD VIH VIL IIH IIL VREF5IN VIH VIL IL VREF3IN VIH VIL IL VIH VIL Hys IIL IIH VIH VIL Hys IIL HIGH-level input voltage LOW-level input voltage Input leakage HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage LOW Input leakage HIGH HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage LOW VIL = 0 V 400 -88 -26 VIL = 0 V VIH = 5VSB 400 -88 -1 0.7*5VSB 0.2*5VSB -26 1 -1 0.7*5VSB 0.2*5VSB 2.2 0.8 1 V V A V V mV A A V V mV A HIGH-level input voltage LOW-level input voltage Input leakage -1 0.85*V5P 0_STBY 0.2*V5P 0_STBY 1 V V A HIGH-level input voltage LOW-level input voltage Input leakage HIGH Input leakage LOW VIL = 0 V -1 -88 2.2 0.8 1 -26 V V A A HIGH-level input voltage LOW-level input voltage Input leakage Input hysteresis -1 400 2.2 0.8 1 V V A mV HIGH-level input voltage LOW-level input voltage Input leakage LOW Input leakage HIGH VIL = 0 V -88 -1 2.0 0.8 -26 1 V V A A HIGH-level input voltage LOW-level input voltage Input leakage HIGH LOW-level output voltage HIGH-level output voltage Input leakage LOW IOL = 6 mA IOH = -3 mA 2.4 -88 -26 -1 2.0 0.8 1 0.4 V V A V V A PARAMETER TEST CONDITION MIN Tamb = 0 C to +70 C TYP MAX UNIT
PRIMARY_HD
SECONDARY_HD
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS SYMBOL IIH SCSI VIH VIL Hys IIL IIH FPRST VIH VIL Hys IIL IIH PWRGD_PS VIH VIL Hys IIL IIH VIH VIL IL IIH VIH VIL IL VCCP_Vref VIH VIL IIL VCCP_Vref HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage LOW Input leakage HIGH HIGH-level input voltage LOW-level input voltage Input leakage Input leakage HIGH-level input voltage LOW-level input voltage Input leakage Bias voltage HIGH-level input voltage LOW-level input voltage Input leakage Bias voltage VIL = 0 V VIH = 5 V Part is strapped for GP mode Part is strapped for GP mode Part is strapped for GP mode GP mode FLUSH mode FLUSH mode FLUSH mode FLUSH mode -1 0.95 -1 1.95 1.5 0.4 1 1.1 -88 -1 2.4 0.8 1 2.1 VIL = 0 V VIH = 5VSB 400 -88 -1 2.2 0.8 -26 1 -26 1 0.7*5VSB 0.2*5VSB V V mV A A V V A A V V A V V V A V HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage LOW Input leakage HIGH VIL = 0 V VIH = 5VSB 400 -88 -1 -26 1 0.7*5VSB 0.2*5VSB V V mV A A HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage LOW Input leakage HIGH VIL = 0 V VIH = 5VSB 400 -88 -1 -26 1 0.7*5VSB 0.2*5VSB V V mV A A PARAMETER Input leakage HIGH TEST CONDITION MIN VIH = 5VSB -1 Tamb = 0 C to +70 C TYP 1 MAX A UNIT
GPO_FLUSH_CACHE/GP2_IN
INIT / GP1_INA (GP Mode)
INIT / GP1_INA (Flush Mode)
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS SYMBOL A20M / GP1_INB VIH VIL IIL VCCP_Vref VIH VIL IL VCCP_Vref CLK_IN VIH VIL Hys IL SEL_33_66 VIH VIL Hys IIH IIL SLP_S3 VIH VIL Hys IL SLP_S5 VIH VIL Hys IL VIH VIL Hys IIH IIL TEST_EN VIH VIL Hys IIH IIL HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage Input leakage VIL = 0 V VIH = 5VSB 400 -1 20 1 88 0.7*5VSB 0.2*5VSB V V mV A A HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage Input leakage VIH = 3VSB VIL = 0 V 400 -1 -88 1 -26 400 -1 2.0 0.8 1 2.2 0.8 V V mV A V V mV A A HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage 400 -1 1 2.2 0.8 V V mV A HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage Input leakage VIL = 0 V 400 -1 -88 1 -26 2.0 0.8 V V mV A A HIGH-level input voltage LOW-level input voltage Input hysteresis Input leakage 250 -1 1 2.2 0.8 V V mV A HIGH-level input voltage LOW-level input voltage Input leakage Bias voltage HIGH-level input voltage LOW-level input voltage Input leakage Bias voltage FLUSH mode FLUSH mode FLUSH mode FLUSH mode GP mode GP mode GP mode GP mode -1 1.95 -1 0.95 2.4 0.8 1 2.1 1.5 0.4 1 1.1 V V A V V V A V PARAMETER TEST CONDITION MIN Tamb = 0 C to +70 C TYP MAX UNIT
CPU_PRESENT
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS SYMBOL HSYNC_3V VIH VIL IL VSYNC_3V VIH VIL IL GRN_BLNK VIH VIL IIH IIL YLW_BLNK VIH VIL IIH IIL GP3_IN VIH VIL IL AUD_RST VOL VOH IOZ AUD_SHDN VOL VOH IOZ REF5V VOUT5 VOUT3 IOUTL VOUT5 VOUT3 IOUTL HD_LED VOL IOZ LOW-level output voltage Off state output current IOL = 12 mA -1 0.4 1 V A LOW-level output voltage HIGH-level output voltage Off state output current LOW-level output voltage HIGH-level output voltage Off state output current V_5P0_STBY > 1.5 V V_5P0_STBY > 1.5 V VREF5in > 1.5 V VREF3in > 1.5 V VREF5in - 0.05 VREF3in - 0.05 -20 V_5P0_STBY - 0.05 V_5P0_STBY - 0.05 -20 VREF5in + 0.05 VREF3in + 0.05 20 V_5P0_STBY + 0.05 V_5P0_STBY + 0.05 20 V V A V V A LOW-level output voltage HIGH-level output voltage Off state output current IOL = 6 mA IOH = -6 mA 2.4 -1 1 0.4 V V A LOW-level output voltage HIGH-level output voltage Off state output current IOL = 6 mA IOH = -3 mA 2.4 -1 1 0.4 V V A HIGH-level input voltage LOW-level input voltage Input leakage -1 2.2 0.8 1 V V A HIGH-level input voltage LOW-level input voltage Input leakage Input leakage VIL = 0 V -1 -88 2.0 0.8 1 -26 V V A A HIGH-level input voltage LOW-level input voltage Input leakage Input leakage VIL = 0 V -1 -88 2.2 0.8 1 -26 V V A A HIGH-level input voltage LOW-level input voltage Input leakage -1 2.2 0.8 1 V V A HIGH-level input voltage LOW-level input voltage Input leakage -1 2.2 0.8 1 V V A PARAMETER TEST CONDITION MIN Tamb = 0 C to +70 C TYP MAX UNIT
REF5V_STBY
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS SYMBOL IDE_RSTDRV VOL VOH IOZ VOL VOH IOZ PRWGD_3V VOL VOH IOZ VOL IOZ VOL IOZ VOL IOZ VOL IOZ VOL VOH IOZ PS_ON VOL IOZ RSMRST VOL VOH IOZ VTRIP VOL IOZ LOW-level output voltage HIGH-level output voltage Off state output current 5VSB LOW trip voltage LOW-level output voltage Off state output current IOL = 6 mA -1 IOL = 6 mA IOH = -3 mA 2.4 -1 1.8 1 3.5 0.4 1 0.4 V V A V V A LOW-level output voltage Off state output current IOL = 6 mA -1 0.4 1 V A LOW-level output voltage HIGH-level output voltage Off state output current LOW-level output voltage Off state output current LOW-level output voltage Off state output current LOW-level output voltage Off state output current LOW-level output voltage Off state output current LOW-level output voltage HIGH-level output voltage Off state output current IOL = 6 mA IOH = -6 mA 2.4 -1 1 IOL = 6 mA -1 IOL = 6 mA -1 IOL = 12 mA -1 IOL = 12 mA -1 IOL = 6 mA IOH = -3 mA 2.4 -1 1 0.4 1 0.4 1 0.4 1 0.4 1 0.4 0.4 V V A V A V A V A V A V V A LOW-level output voltage HIGH-level output voltage Off state output current LOW-level output voltage HIGH-level output voltage Off state output current IOL = 6 mA IOH = -3 mA 2.4 -1 1 IOL = 6 mA IOH = -6 mA 2.4 -1 1 0.4 0.4 V V A V V A PARAMETER TEST CONDITION MIN Tamb = 0 C to +70 C TYP MAX UNIT
PCIRST_OUT
INIT_OUT / GP2_OUT
FLUSH_OUT_CPU / GP1_OUT
BACKFEED_CUT
FLUSH_OUT_FWH
LATCHED_BACKFEED_CUT
SCK_BJT_GATE
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS SYMBOL 3V_DDCSDA VOL IH IOZ VOL IH IOZ 3V_DDCSCL VOL IH IOZ 5V_DDCSCL VOL IH IOZ HSYNC_5V VOL VOH IOZ VSYNC_5V VOL VOH IOZ VOL IOZ GP3_OUT VOL IOZ LOW-level output voltage Off state output current IOL = 6 mA -1 1 A LOW-level output voltage HIGH-level output voltage Off state output current LOW-level output voltage Off state output current IOL = 24 mA -1 IOL = 6 mA IOH = -6 mA 3.8 -1 1 0.4 1 0.4 V V A V A LOW-level output voltage HIGH-level output voltage Off state output current IOL = 6 mA IOH = -6 mA 3.8 -1 1 0.4 V V A LOW-level output voltage Input leakage Off state output current IOL = 6 mA 3V_DDCSCL = VDD -1 -1 0.4 2.5 1 V A A LOW-level output voltage Input leakage Off state output current IOL = 6 mA 5V_DDCSCL = VDD -1 -1 0.4 2.5 1 V A A LOW-level output voltage Input leakage Off state output current LOW-level output voltage Input leakage Off state output current IOL = 6 mA 3V_DDCSDA = VDD -1 -1 IOL = 6 mA 5V_DDCSDA = VDD -1 -1 0.4 2.5 1 0.4 2.5 1 V A A V A A PARAMETER TEST CONDITION MIN Tamb = 0 C to +70 C TYP MAX UNIT
5V_DDCSDA
GRN_LED / YLW_LED
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
AC CHARACTERISTICS
VCC1 = 3.3 V; VCC = 5.0 V LIMITS SYMBOL tRESET tRESET_FALL PARAMETER MIN RSMRST RSMRST Propagation Delay AUD_EN to AUD_RST PCIRST to AUD_RST PCIRST to IDE_RSTDRV PCIRST to PCIRST_OUT Propagation Delay MUTE_AUD to MUTE_SHDN Propagation Delay PWRGD_PS to PWRGD_3V FPRST to PWRGD_3V Propagation Delay HSYNC_3V to HSYNC_5V VSYNC_3V to VSYNC_5V Propagation Delay PWRGD_PS to SCK_BJT_GATE FPRST to SCK_BJT_GATE Open Drain Prop Delay PRIMARY_HD to HD_LED PRIMARY_HD to HD_LED PRIMARY_HD to HD_LED Open Drain Prop Delay GP1_INA to GP1_OUT GP2_INA to GP1_OUT Open Drain Prop Delay GP2_IN to GP2_OUT Open Drain Prop Delay GP3_IN to GP3_OUT Open Drain Prop Delay SLP_S3 to BACKFEED_OUT PRWGD_PS to BACKFEED_OUT Open Drain Prop Delay CPU_PRESENT to PS_ON Open Drain Prop Delay SLP_S3 to PS_ON Open Drain Prop Delay BACKFEED_OUT to LATCHED_BACKFEED_OUT Open Drain Prop Delay SLP_S5 to YLW_LED SLP_S5 to GRN_LED YLW_BLNK to YLW_LED GRN_BLNK to GRN_LED Open Drain Prop Delay 3V_DDOSDA to 5V_DDOSDA 3V_DDOSDA to 5V_DDOSDA Rise and Fall Times HSYNC_5V VSYNC_5V Rise and Fall Times LATCHED_BACKFEED_OUT 4.0 Tamb = 0 _C to +70 _C TYP MAX 100 100 ms ns UNITS NOTES
tPHL/tPLH
1.0
11.0
ns
tPLH/tPHL tPLH/tPHL
2.5
6.0
ns
4.5
11.0
ns
tPLH/tPHL
2.0
5.0
ns
tPLH/tPHL
1.0
6.0
ns
tPLZ/tPZL
1.0
5.0
ns
tPLZ/tPZL tPLZ/tPZL tPLZ/tPZL tPLZ/tPZL tPLZ/tPZL tPLZ/tPZL tPLZ/tPZL
3.0
25.0
ns
3.0 1.0
7.0 4.0
ns ns
1.0
6.0
ns
2.0 2.0
10.0 10.0
ns ns
2.0
11.0
ns
tPLZ/tPZL
1.0
5.0
ns
tPLZ/tPZL
1.0
5.0
ns
tr, tf tr, tf
3.5
ns s
1.0
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Philips Semiconductors
Product data
Glue chip 4
PCA9504A
WAVEFORMS
VIH INPUT VM VM VIL tPLH tPHL VOH OUTPUT VM VM VOL OUTPUT VM VM INPUT VM tPHL VM tPLH
SF01443
SW00720
Waveform 3.
VI VDD INPUT VM
Waveform 1.
VI INPUT GND VM
GND VDD tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL VM VX tPZL OUTPUT LOW-to-OFF OFF-to-LOW VOL
tPLZ
tPZL
VM VX
tPHZ
tPZH
SW00721
tPHZ tPZH
Waveform 4.
SW00722
Waveform 2.
2004 May 11
14
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
5V REFERENCE GENERATION
Supply VREF5IN < VREF3IN VREF5IN > VREF3IN VREF3IN VREF5IN REF5V
3.3 V
VREF3IN
5V
VREF5IN
5V
3.3 V
REF5V
SW00580
Figure 1. REF5V when VREF3IN ramps before VREF5IN
3.3 V
VREF3IN
5V
VREF5IN
5V
REF5V
SW00581
Figure 2. REF5V when VREF5IN ramps before VREF3IN
2004 May 11
15
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
5V STANDBY REFERENCE GENERATION
Standby Supply V_5PO_STBYtV_3P3_STBY V_5PO_STBYuV_3P3_STBY V_3P3_STBY V_5PO_STBY REF5V_STBY
3.3 V
V_3P3_STBY
5V
V_5P0_STBY
5V
3.3 V
REF5V_STBY
SW00582
Figure 3. REF5V_STBY when V_3P3_STBY ramps before V_5PO_STBY
V_3P3_STBY
V_5P0_STBY
REF5V_STBY
SW00583
Figure 4. REF5V_STBY when V_5PO_STBY ramps before V_3P3_STBY
2004 May 11
16
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
FLUSH OUT* / INIT OUT* CIRCUIT
V_VCCP VCC3
1 k
1 k
1 k
H_INIT_OUT* ICH_A20M* CPU H_FLUSH_OUT_CPU* ICH_INIT* GLUE CHIP
GPO_FLUSH_CACHE*
H_FLUSH_OUT_FWH*
FWH VCCP 50 VCCP_VREF
100
1 F
SW00584
Figure 5. Block diagram for FLUSH_OUT*/INIT_OUT* circuit
Case 1 2 3 4 5 6 1 1 X X 0 0
A20M*
GPO FLUSH CACHE* falling edge falling edge 1 1 falling edge falling edge 0 1 0 1 1 0
INIT*
FLUSH OUT CPU* 0 (for t1) 0 (for t1) Hi-Z Hi-Z Hi-Z Hi-Z
FLUSH OUT FWH* 0 (for t1) 0 (for t1) Hi-Z Hi-Z Hi-Z Hi-Z
INIT OUT* 0, Hi-Z, then 0 (delayed by t1-t, then active for 2*t) Hi-Z, 0 (delayed by t1-t, then active for 2*t) 0 Hi-Z Hi-Z 0
NOTE: 1. Nominal value timings with tolerances are listed in the DC Characteristics table for t and t1. All Hi-Z outputs are shown as 1's or HIGH in the following diagrams.
2004 May 11
17
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
t1 FLUSH_OUT_CPU*
t1 FLUSH_OUT_FWH*
t
t
INIT_OUT*
SW00585
Figure 6. Waveforms for Case 1
A20M*
GPO_FLUSH_CACHE*
INIT*
t1 FLUSH_OUT_CPU*
t1 FLUSH_OUT_FWH* t t
INIT_OUT*
SW00586
Figure 7. Waveforms for Case 2
2004 May 11
18
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00587
Figure 8. Waveforms for Case 3
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00588
Figure 9. Waveforms for Case 4
2004 May 11
19
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00589
Figure 10. Waveforms for Case 5
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00590
Figure 11. Waveforms for Case 6
2004 May 11
20
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
t1
INIT*
t1 FLUSH_OUT_CPU*
t1 FLUSH_OUT_FWH* t t
INIT_OUT*
t
SW00591
Figure 12. Waveforms for Case 7
A20M*
GPO_FLUSH_CACHE*
INIT*
t1 FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
t1
t
t
INIT_OUT*
SW00592
Figure 13. Waveforms for boundary GPO_FLUSH_CACHE* Case
* Timings should remain the same for both a 66 MHz or 33 MHz
CLK_IN input. * The boundary condition for INIT listed above, is a special case where immediately following the FLUSH_OUT*, INIT_OUT* cycle, the ICH2 asserts INIT* into the Glue Chip. * The boundary condition for GPO_FLUSH_CACHE* listed above, is a special case where immediately following the first assertion of GPO_FLUSH_CACHE*, the GPO is de-asserted, then re-asserted again before the timings have had a chance to complete. NOTE: 1. Nominal timing values with tolerances are listed in the DC Characteristics table.
GPO_FLUSH_CACHE* - input to logic, GPO from the ICH2, programmed active LOW. INIT* - input to logic, INIT* signal from the ICH2. A20M* - input to logic, A20M* signal from the ICH2. FLUSH_OUT_CPU* - output of logic, route to CPU FLUSH* pin. FLUSH_OUT_CPU* - output of logic, routed to FWH INIT* pin. INIT_OUT* - output of logic, routed to CPU INIT* pin.
2004 May 11
21
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
T1 BACKFEED_CUT* T2
SLP_S5*
LATCHED_BACKFEED_CUT
SW00593
Figure 14. Power up signal sequencing Power up signal sequencing is shown in Figure 14. BACKFEED_CUT* is following the power rail up to its final value. LATCHED_BACKFEED_CUT should stay LOW, never turning on. SLP_S5* goes to its HIGH value when the power rails have stabilized, X25 msec after power on. BACKFEED_CUT* is pulled LOW a period T1 after SLP_S5* goes HIGH. T1 can be as short as 1msec. Typical measured values are X200 msec. T1 and T2 are guaranteed by the inherent design of the system and are not controlled by Glue Chip.
SLP_S5* Tpropr Tpropf
BACKFEED_CUT* Tr LATCHED_BACKFEED_CUT Tf
SW00594
Figure 15. 1st sequence timing The first possible sequence is with SLP_S5*staying HIGH and BACKFEED_CUT* transitioning from LOW to HIGH, remaining HIGH for an undetermined period and then going back to LOW and the system is back at the end of the power-up sequence. The power-up sequence is shown in Figure 15. During these BACKFEED_CUT* transitions, the propagation delays, rise and fall times, and going into regulation times LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time.
T3
T4
BACKFEED_CUT*
SLP_S5* Tpropr Tpropf LATCHED_BACKFEED_CUT
Tr
Tf
SW00595
Figure 16. 2nd sequence timing Signal sequencing for the second possible sequence is shown in Figure 16. BACKFEED_CUT* goes from LOW to HIGH and SLP_S5* goes from HIGH to LOW, 30 sec to 65 sec (T3) later. LATCHED_BACKFEED_CUT goes HIGH when BACKFEED_CUT* goes HIGH and then LATCHED_BACKFEED_CUT returns to LOW when SLP_S5* goes LOW. BACKFEED_CUT* stays HIGH and SLP_S5* stays LOW for an indeterminate time and then SLP_S5* will go HIGH. A minimum of 1msec (T4) later, BACKFEED_CUT* will go LOW and the system is back at the end of the power-up sequence. Typical measured values of T4 are X250 msec. During all transitions, the propagation delays, rise and fall times, and going into regulation times for LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time. 22
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
RSMRST* GENERATION
RSMRST* is a delayed 3.3 V hysteresis copy of V_5PO_STBY. RSMRST* is delayed going inactive from the rising edge of V_5PO_STBY by 32 ms, nominal. This delay starts when V_5PO_STBY hits the trip point. There is minimal delay on the falling edge.
max V_5P0_STBY min VTRIP
treset
RSMRST*
SW00596
Figure 17. Resume reset functionality
V_5P0_STBY
tRESET tRESET_FALL
RSMRST*
SW00597
Figure 18. Resume reset functionality during brown out
2004 May 11
23
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
AUDIO-DISABLE
AUD_EN 0 0 1 1 PCIRST 0 1 0 1 AUD_RST 0 0 0 1
MUTE AUDIO CIRCUIT
MUTE_AUD 0 1 AUD_SHDN 1 0
HD SINGLE COLOR LED DRIVER
PRIMARY_HD 0 0 X X 1 SECONDARY_HD 0 X 0 X 1 SCSI 0 X X 0 1 HD_LED 0 0 0 0 HI-Z
IDE RESET SIGNAL GENERATION AND PCRIST DRIVE STRENGTH
PCIRST 0 1 IDE_RSTDRV1 0 1 PCIRST_OUT 0 1
NOTE: 1. IDE_RSTDRV is a 5 V copy of PCIRST. PCIRST_OUT is a 3.3 V copy of PCIRST.
PWRGD SIGNAL GENERATION
FPRST 0 0 1 1 PWRGD_PS 0 1 0 1 PWRGD_3V 0 0 0 1
FLUSH_OUT / INIT_OUT CIRCUIT
CASE 1 2 3 4 5 6 A20M 1 1 X X 0 0 GPO_FLUSH_CACHE Falling edge Falling edge 1 1 Falling edge Falling edge INIT 0 1 0 1 1 0 FLUSH_OUT_CPU 0(for t1) 0(for t1) Hi-Z Hi-Z Hi-Z Hi-Z FLUSH_OUT_FWH 0(for t1) 0(for t1) Hi-Z Hi-Z Hi-Z Hi-Z INIT_OUT 0, Hi-Z, then 0 (delayed by t1-t, then active for 2*t) Hi-Z, 0 (delayed by t1-t, then active for 2*t) 0 Hi-Z Hi-Z 0
CLK_IN AND SEL_33_66
SEL_33_66 0 1 CLK_IN RATE 66 MHz 33 MHz
2004 May 11
24
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
CLK_IN B2 CLK SEL_33_66
SW00603
Figure 19.
GP_IN/GP_OUT GENERAL PURPOSE GATES
GP1_INA 0 0 1 1 GP1_INB 0 1 0 1 GP1_OUT 1 1 1 0
GP_IN/GP_OUT GENERAL PURPOSE GATES (continued)
GP2_IN 0 1 GP2_OUT 1 0
GP_IN/GP_OUT GENERAL PURPOSE GATES (continued)
GP3_IN 0 1 GP3_OUT 0 1
POWER SEQUENCING / BACKFEED_CUT
PWRGD_PS 0 0 1 1 SLP_S3 0 1 0 1 BACKFEED_CUT HI-Z HI-Z HI-Z 0
POWER SUPPLY TURN-ON CIRCUIT
SLOTOCC 0 0 1 1 SLP_S3 0 1 0 1 SLP_S3A Hi-Z 0 Hi-Z Hi-Z
RAMBUS_SCK_BJT
PWRGD_3V 0 1 SCK_BJT_GATE Hi-Z 0
2004 May 11
25
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
VGA DCC VOLTAGE TRANSLATION
3V_DDCSDA 0 0 1 1 3V_DDCSCL 0 1 0 1 5V_DDCSDA 0 0 1 1 5V_DDCSCL 0 1 0 1
HSYNC / VSYNC VOLTAGE TRANSLATION
HSYNC_3V 0 1 HSYNC_5V 0 1 VSYNC_3V 0 1 VSYNC_5V 0 1
POWER LED DRIVER
YLW_BLNK 0 0 1 1 SLP_S5 0 1 0 1 YLW_LED 0 0 0 HI-Z GRN_BLNK 0 0 1 1 SLP_S5 0 1 0 1 GRN_LED 0 0 0 Hi-Z
2004 May 11
26
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
2004 May 11
27
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
REVISION HISTORY
Rev _5 Date 20040511 Description Product data (9397 750 13279). Supersedes data of 2003 Nov 10 (9397 750 12288). Modifications:
* Page 24, Audio-disable table: AUD_EN column (reading veritcally) changed from `0000' to `0011'.
_4 _3 20031110 20030328 Product data (9397 750 12288); ECN 853-2206 30409 dated 10 October 2003. Supersedes data of 28 March 2003 (9397 750 09602). Product data (9397 750 09602); ECN: 853-2206 27930 (2003 Mar 28)
2004 May 11
28
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 05-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 13279
Philips Semiconductors
2004 May 11 29

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